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Genesys Logic, Inc.
GL811S
USB 2.0 to ATA/ATAPI Bridge Controller
Datasheet Revision 1.02 Apr. 13, 2007
GL811S USB2.0 to ATA/ATAPI Bridge Controller
Copyright:
Copyright (c) 2007 Genesys Logic Incorporated. All rights reserved. No part of the materials may be reproduced in any form or by any means without prior written consent of Genesys Logic, Inc.
Disclaimer:
ALL MATERIALS ARE PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NO LICENSE OR RIGHT IS GRANTED UNDER ANY PATENT OR TRADEMARK OF GENESYS LOGIC INC.. GENESYS LOGIC HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS IN REGARD TO MATERIALS, INCLUDING ALL WARRANTIES, IMPLIED OR EXPRESS, OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY. IN NO EVENT SHALL GENESYS LOGIC BE LIABLE FOR ANY DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES RESULTING FROM LOSS OF INFORMATION OR PROFITS. PLEASE BE ADVISED THAT THE MATERIALS MAY CONTAIN ERRORS OR OMMISIONS. GENESYS LOGIC MAY MAKE CHANGES TO THE MATERIALS OR TO THE PRODUCTS DESCRIBED THEREIN AT ANY TIME WITHOUT NOTICE.
Trademarks:
is a registered trademark of Genesys Logic, Inc. All trademarks are the properties of their respective owners.
Office:
Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Revision History
Revision 1.00 1.01 1.02 Date 03/09/2006 05/25/2006 04/13/2007 First release Modify GL811S 48 Pin TQFP Package, Figure 7.2, p.37 Remove 48Pin TQFP Pinout, p.9 and 48Pin TQFP Dimension, p.35 Description
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
TABLE OF CONTENTS CHAPTER 1 GENERAL DESCRIPTION................................................... 7 CHAPTER 2 FEATURES .............................................................................. 8 CHAPTER 3 PIN ASSIGNMENT ................................................................ 9 3.1 PINOUTS...................................................................................................... 9 3.2 PIN LIST.................................................................................................... 11 3.3 PIN DESCRIPTIONS ................................................................................... 12 CHAPTER 4 BLOCK DIAGRAM.............................................................. 16 CHAPTER 5 FUNCTION DESCRIPTION ............................................... 17 5.1 UTM......................................................................................................... 17 5.2 SIE............................................................................................................ 17 5.3 EP0/EP3 FIFO ........................................................................................ 17 5.4 BULK FIFO .............................................................................................. 17 5.5 IDE INTERFACE ....................................................................................... 17 5.6 OPERATION REGISTER............................................................................. 17 5.7 SPI INTERFACE ........................................................................................ 17 CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 18 6.1 ABSOLUTE MAXIMUM RATINGS.............................................................. 18 6.2 TEMPERATURE CONDITIONS ................................................................... 18 6.3 DC CHARACTERISTICS ............................................................................ 18 6.3.1 I/O Type digital pins ....................................................................... 18 6.3.2 D+/ D- ............................................................................................... 19 6.3.3 Switching Characteristics............................................................... 19 6.4 AC CHARACTERISTICS- ATA/ ATAPI ................................................... 19 6.4.1 Register Transfers / PIO Data Transfers ..................................... 21 6.4.2 Multiword DMA data transfer ...................................................... 23 6.4.3 Ultra DMA data transfer................................................................ 27 6.5 AC CHARACTERISTICS - USB 2.0............................................................ 34 CHAPTER 7 PACKAGE DIMENSION..................................................... 35 CHAPTER 8 ORDERING INFORMATION ............................................ 37
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
LIST OF FIGURES
FIGURE 3.1 - 48 PIN LQFP PINOUT DIAGRAM.................................................................... 9 FIGURE 3.2 - 64 PIN LQFP PINOUT DIAGRAM.................................................................. 10 FIGURE 4.1 - BLOCK DIAGRAM ......................................................................................... 16 FIGURE 6.1 - INITIATING A MULTIWORD DMA DATA BURST.......................................... 24 FIGURE 6.2 - SUSTAINING A MULTIWORD DMA DATA BURST ........................................ 25 FIGURE 6.3 - DEVICE TERMINATING A MULTIWORD DMA DATA BURST....................... 25 FIGURE 6.4 - HOST TERMINATING A MULTIWORD DMA DATA BURST........................... 26 FIGURE 6.5 - INITIATING AN ULTRA DMA DATA-IN BURST ............................................ 28 FIGURE 6.6 - SUSTAINED ULTRA DMA DATA-IN BURST.................................................. 28 FIGURE 6.7 - HOST PAUSING AN ULTRA DMA DATA-IN BURST...................................... 29 FIGURE 6.8 - DEVICE TERMINATING AN ULTRA DMA DATA-IN BURST ......................... 29 FIGURE 6.9 - HOST TERMINATING AN ULTRA DMA DATA-IN BURST............................. 30 FIGURE 6.10 - INITIATING AN ULTRA DMA DATA-OUT BURST ...................................... 31 FIGURE 6.11 - SUSTAINED ULTRA DMA DATA-OUT BURST ............................................ 31 FIGURE 6.12 - DEVICE PAUSING AN ULTRA DMA DATA-OUT BURST............................. 32 FIGURE 6.13 - HOST TERMINATING AN ULTRA DMA DATA-OUT BURST ......................... 33 FIGURE 6.14 - DEVICE TERMINATING AN ULTRA DMA DATA-OUT BURST.................... 34 FIGURE 7.1 - GL811S 48 PIN LQFP PACKAGE................................................................ 35 FIGURE 7.2 - GL811S 64 PIN LQFP PACKAGE................................................................ 36
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
LIST OF TABLES
TABLE 3.1 - 48 PIN LIST..................................................................................................... 11 TABLE 3.2 - 64 PIN LIST..................................................................................................... 11 TABLE 3.3 - 48 PIN DESCRIPTIONS.................................................................................... 12 TABLE 3.4 - 64 PIN DESCRIPTIONS .................................................................................... 13 TABLE 6.1 - MAXIMUM RATINGS ...................................................................................... 18 TABLE 6.2 - TEMPERATURE CONDITIONS ......................................................................... 18 TABLE 6.3 - I/O TYPE DIGITAL PINS .................................................................................. 18 TABLE 6.4 - D+/ D-............................................................................................................. 19 TABLE 6.5 - SWITCHING CHARACTERISTICS .................................................................... 19 TABLE 6.5 - ULTRA DMA DATA BURST TIMING REQUIREMENTS ..................................... 27 TABLE 8.1 - ORDERING INFORMATION ............................................................................. 37
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 1 GENERAL DESCRIPTION
The GL811S is a highly-compatible, low cost USB 2.0 to ATA / ATAPI bridge controller, which integrates Genesys Logic own design high speed UTMI (USB 2.0 Transceiver Macrocell Interface) transceiver. As a one-chip solution which complies with Universal Serial Bus specification rev. 2.0 and ATA / ATAPI-6 specification rev 1.0, the GL811S can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811S controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811S can support not only plug and play but also Windows XP/ 2000/ ME default driver. The GL811S uses 12MHz crystal and slew-rate controlled pads to reduce the EMI issue. With 48-pin LQFP (7mmX7mm) package, the GL811S is the best cost/ performance solution to fit different situations in the USB 2.0 high speed storage class applications such as Hard Disk, CD-ROM, CD-R / RW and DVD-ROM.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 2 FEATURES
* Complies with Universal Serial Bus specification rev. 2.0. * Complies with ATA/ATAPI-6 specification rev 1.0. * Complies with USB Storage Class specification ver.1.0. (Bulk only protocol) * Operating system supported: Win XP / 2000 / Me / 98 / 98SE; Mac OS 9.X / 10.X. * Integrated USB 2.0 Transceiver Macrocell Interface (UTMI) transceiver and Serial Interface Engine (SIE). * Support 4 endpoints: Control (0) / Bulk Read (1) / Bulk Write (2) / Interrupt (3). * 64 / 512 bytes Data Payload for full / high speed Bulk Endpoint. * Support 16-bit Multiword DMA mode and Ultra DMA mode interface (Ultra 33 / 66). * Embedded Turbo 8051. * ROM size: 12k words; RAM size: 1280 bytes. (Bulk Buffer: 512 words, MC RAM: 256 bytes) * Supports Power Down mode and USB suspend indicator. * Supports USB 2.0 TEST mode features. * Supports 4 GPIOs for programmable AP (48 pin package). * Supports 8 GPIOs for programmable AP (64 pin package). * Supports device power control for power on/off when running suspend mode. * Supports 32 bit and 48 bit LBA hard disk. * Provides LED indicator for Full Speed and High Speed (only for 64 pin package). * Using 12 MHz external clock to provide better EMI. * 3.3V I/Os (5V tolerant) 5V tolerance pad for IDE interface. * Operates at 5V voltage (built-in 5V to 3.3V & 3.3V to 1.8V regulator) * Supports Wakeup ability. * Available in 48-pin/64-pin LQFP package types. * Provides SPI interface (only for 64 pin package). * Provides UART interface (only for 64 pin package).
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 3 PIN ASSIGNMENT
3.1 Pinouts
D_PWR_CTL
3V3_OUT
DMACK_
INTRQ
5V_IN
TEST 26 11 DD8
CS0_
CS1_
DA1
DA0
DA2
36
35
34
33
32
31
30
29
28
27
10
PIO0
DD3
DD4
DD5
DD9
DD6
DD12
DD11
DD10
Figure 3.1 - 48 Pin LQFP Pinout Diagram
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DVDD1
DD7
12
1
2
3
4
5
6
7
8
9
25
XI
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
D_PWR_CTL
3V3_OUT
DMACK_
INTRQ
DGND 34
5V_IN
U_RX
U_TX
TEST
CS0_
CS1_
DA1
DA2
DA0
NC
47
46
45
44
43
42
41
40
39
38
37
36
35
IORDY NC DIOR_ DIOW_ DMARQ DD15 DGND DVDD DD0 DD14 DD1 DD13 DD2
GPIO1
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
33
48
XI
32 31 30 29 28 27 26 25
XO
X_POWER
AVDD1 RREF AGND1 DP DM AVDD3 AGND DGND RESET#
USB_PWR HD_RST#
GL811S
LQFP - 64
10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
NC NC NC
F_LED H_LED
1
2
3
4
5
6
7
8
DVDD
9
DGND
PIO2
PIO0
DD12
PIO1
DD3
DD11
DD4
DD10
DD5
DD9
DD6
DD8
Figure 3.2 - 64 Pin LQFP Pinout Diagram
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DD7
NC
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GL811S USB2.0 to ATA/ATAPI Bridge Controller 3.2 Pin List
Table 3.1 - 48 Pin List
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type 1 2 3 4 5 6 7 8 9 10 11 12 DD12 DD3 PIO0 DD11 DD4 DD10 DVDD1 DD5
DD9
B B B B B B P B B B B B
13 HD_RST#
O
25 26 27
XI TEST CS1_
I
37 38 39
IORDY DIOR_ DIOW_
I O O I B P B B B B B B
14 USB_PWR B 15 16 17 18 19 20 21 22 RESET# AGND1 AVDD1 DM DP AGND2 VREF AVCC2 I P P B B P A P P B
I O
28 D_PWR_CTL B 29 30 31 32 33 34 35 36 5V_IN 3V3_OUT CS0_ DA2 DA0 DA1 INTRQ DMACK_ P P O O O O I O
40 DMARQ 41 42 43 44 45 46 47 48
DD15 DVDD
DD0 DD14 DD1 DD13 DD2 GPIO1
DD6 DD8 DD7
23 X-POWER 24 XO
Table 3.2 - 64 Pin List
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Name DD12 DD3 PIO2 PIO0 PIO1 DD11 DD4 DD10
DVDD
Type Pin# B B B B B B B B P P B B B B 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Pin Name NC NC NC HD_RST# USB_PWR RESET# DGND AGND AVDD3
DM
Type Pin# 33 34 35 O B I P P P B B P A P 36 37
Pin Name XI DGND NC TEST CS1_
Type Pin#
I
Pin Name IORDY NC DIOR_ DIOW_
DMARQ DD15
Type I O O I B P P B B B B B B
49 50 51
P
I O B P P O O B O O O
52 53 54 55 56 57 58 59 60 61 62
38 D_PWR_CTL 39 40 41 42 43 44 45 46 5V_IN DVDD CS0_ DA2 U_RX U_TX DA0 DA1
DGND DVDD DD0 DD14 DD1 DD13 DD2 GPIO 1
DGND DD5 DD9
DD6
DP AGND1 RREF AVDD1
DD8
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
15 16
DD7 NC
B
31 32
X_POWER XO
P B
47 48
INTRQ DMACK_
I O
63 64
F_LED H_LED
B
B
3.3 Pin Descriptions
Table 3.3 - 48 Pin Descriptions
USB Interface Pin Name VREF DM DP XO XI RESET# TEST Pin# 21 18 19 24 25 15 26 Type A B B B I I (pu) I (pd) Reference Resistor HS DHS D+ Crystal output Crystal input External reset Test mode Input Description
ATA/ATAPI Interface Pin Name Pin# 43,45,47, 2,5,8,10,1 2,11,9,6,4, 1,46,44, 41 13 27,31 33,34,32 35 36 37 38 39 40 Type Description
DD0~15
B (pd) O O O I (pd) O I (pu) O O I (pd)
IDE Data Bus
HD_RST# CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ
Device Reset Chip Select #1,#0 IDE Address #2,#1,#0 IDE interrupt input IDE Acknowledge IDE Ready IDE read signal IDE write signal IDE request
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Miscellaneous Interface Pin Name GPIO 1 PIO0 Pin# 48 3 Type B (pu) B (pd) GPIO GPIO Description
Power / Ground Pin Name 5V_IN DVDD1,X-POW ER,3V3_OUT, DVDD2 AGND1 AGND2 AVCC1 AVCC2 16 20 17 22 P P P P Analog GND Analog GND #1 Analog VDD #3 Analog VDD #1 7,23,30,42 P Digital VDD Pin# 29 Type P 5V input Description
Miscellaneous Pin Name USB_PWR D_PWR_CTL Pin# 14 28 Type B (pu) B (pd) USB power detect HDD power control Description
Table 3.4 - 64 Pin Descriptions
USB Interface Pin Name RREF DM DP XO XI RESET# TEST Pin# 29 26 27 32 33 22 36 Type A B B B I I (pu) I (pd) Reference Resistor HS DHS D+ Crystal output Crystal input External reset Test mode Input Description
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
ATA/ATAPI Interface Pin Name Pin# 57,59,61, 2,7,11,13, 15,14,12, 8,6,1,60, 58,54 20 37,41 45,46,42 47 48 49 51 52 53 Type Description
DD0~15
B (pd) O O O I (pd) O I (pu) O O I (pd)
IDE Data Bus
HD_RST# CS1_, CS0_ DA0~2 INTRQ DMACK_ IORDY DIOR_ DIOW_ DMARQ
Device Reset Chip Select #1,#0 IDE Address #2,#1,#0 IDE interrupt input IDE Acknowledge IDE Ready IDE read signal IDE write signal IDE request
Miscellaneous Interface Pin Name GOPI 1 PIO 0 PIO 1 PIO 2 U_RX U_TX Pin# 62 4 5 3 43 44 Type B (pu) B (pd) B (pd) B (pd) B (pu) O General Purpose IO #1 Program IO #0 Program IO #1 becomes SPIDI when SPI interface is enabled (SPIDI : SPI Data Input) Program I/O #2 becomes SPIDO when SPI interface is enabled (SPIDO : SPI Data Output) UART RXD UART TXD Power / Ground Pin Name 5V_IN DGND DVDD AGND AGND1 AVDD3 Pin# 39 10,23,34,55 9,31,40,56 24 28 25 Type P P P P P P 5V input Digital GND Digital VDD Analog GND Analog GND #1 Analog VDD #3 Description Description
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
AVDD1
30
P
Analog VDD #1
Miscellaneous Pin Name USB_PWR F_LED H_LED D_PWR_CTL Pin# 21 63 64 38 Type B (pu) B (pu) B (pu) B (pd) USB power detect Operation mode indicator (Full-Speed) Operation mode indicator (High-Speed) HDD power control Description
Notation: Type O I B B/I B/O P A SO pu pd odpu
Output Input Bi-directional Bi-directional, default input Bi-directional, default output Power / Ground Analog Automatic output low when suspend Internal pull up Internal pull down Open drain with internal pull up
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 4 BLOCK DIAGRAM
GPIO
8051 Core
2K ROM
Operation Register
IDE Device
IDE Interface
Bulk FIFO
SIE
EP0, EP3 FIFO
SPI Interface
UTM
SPI Device
USB
Figure 4.1 - Block Diagram
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 5 FUNCTION DESCRIPTION
5.1 UTM
The USB 2.0 Transceiver Macrocell, it's the analog circuitry that handles the low level USB protocol and signaling, and shifts the clock domain of the data from the USB 2.0 rate to one that is compatible with the general logic.
5.2 SIE
The Serial Interface Engine, which contains the USB PID and address recognition logic, and other sequencing and state machine logic to handle USB packets and transactions.
5.3 EP0/EP3 FIFO
Endpoint 0/3 FIFO: The Control and Interrupt FIFO. It is composed of TX03FIFO and RX03FIFO, with 64-byte FIFO each, and it is used for endpoint 0/3 data transfer.
5.4 Bulk FIFO
It is constructed in interleaved architecture and composed by two data buffers which is used to store data transferred between USB host and IDE device.
5.5 IDE Interface
The IDE engine is extended from standard ATA / ATAPI protocol. It supports multiword DMA mode, and ultra DMA mode data transfers.
5.6 Operation Register
It is a register space to store status information and to control the functions of GL811S by 8051.
5.7 SPI Interface
The Serial Peripheral Interface is a serial, synchronous communication protocol. It is compatible with Motorola's SPI specifications.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 6 ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
Table 6.1 - Maximum Ratings
Symbol VCC VI VI/O VAI/O VESD TA DC supply voltage DC input voltage DC input voltage range for I/O DC input voltage for USB D+/D- pins Static discharge voltage Ambient Temperature Parameter Min. +3.0 -0.3 -0.3 -0.3 4000 0 100 Max. +3.6 VCC + 0.3 VCC + 0.3 VCC + 0.3 Unit V V V V V
o
C
6.2 Temperature Conditions
Table 6.2 - Temperature Conditions
Item Storage Temperature Operating Temperature
o
Value -50 C ~ 150 oC 0 oC ~ 70 oC
6.3 DC Characteristics 6.3.1 I/O Type digital pins
Table 6.3 - I/O Type digital pins
Parameter Current sink @ VOL = 0.4V Current output @ VOH = 2.4V (TTL high) Falling slew rate at 30 pF loading capacitance Rising slew rate at 30 pF loading capacitance Schmitt trigger low to high threshold point Schmitt trigger low to high threshold point Pad internal pull up resister Pad internal pull down resister Min. 10.58 14.74 0.56 0.58 1.4 1.4 37.87K 29.85K Typ. 14.21 27.46 0.91 0.91 1.5 1.5 64.7K 59.45K Max. 16.87 43.0 1.28 1.72 1.6 1.6 108.11K 134.26K Unit mA mA V/ns V/ns V V Ohms Ohms
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Page 18
GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.3.2 D+/ DTable 6.4 - D+/ DParameter D+/D- static output LOW (RL of 1.5K to VCC ) D+/D- static output HIGH (RL of 15K to GND ) Differential input sensitivity Single-ended receiver threshold Transceiver capacitance Hi-Z state data line leakage Driver output resistance -10 28 Min. 0 2.8 0.2 0.8 2.0 20 +10 43 Typ. Max. 0.3 3.6 Unit V V V V pF A Ohms
6.3.3 Switching Characteristics
Table 6.5 - Switching Characteristics
Parameter X1 crystal frequency X1 cycle time D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading 4 4 Min. 11.97 Typ. 12 83.3 20 20 Max. 12.03 Unit MHz ns ns ns
6.4 AC Characteristics- ATA/ ATAPI
The GL811S complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes:
1.
DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When a Multiword DMA transfer is enabled as indicated by IDENTIFY DEVICE or IDENTIFY PACKET DEVICE data, this data transfer protocol shall be used for the data transfers associated with these commends. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.) - Ultra DMA: Ultra DMA Is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. (Please refer to the ATA / ATAPI-6 specification rev 1.0 for more information.)
Following listed the symbols and their respective definitions that are used in the timing diagram:
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
-
Signal transition (asserted or negated) Data transition (asserted or negated) Data valid Undefined but not necessarily released Asserted, negated or released Released The "other" condition if a signal is shown with no change
-
All signals are shown with the asserted condition facing to the top of the page. The negated condition is shown towards the bottom of the page relative to the asserted condition. The interface uses a mixture of negative and positive signals for control and data. The terms asserted and negated are used for consistency and are independent of electrical characteristics. In all timing diagrams, the lower line indicates negated, and the upper line indicates asserted. The following illustrates the representation of a signal named Test going from negated to asserted and back to negated, based on the polarity of the signal.
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Page 20
GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.1 Register Transfers / PIO Data Transfers
Notes: 1. Device address consists of signals CS0_, CS1_ and DA(2:0). 2. Data consists of IODD(7:0). 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIOR_ or DIOW_. The assertion and negation of IORDY are described as following: 3.1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3.2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3.3 Device negates IORDY before tA, IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for tRD before asserting IORDY. 4. DMACK_ shall remain negated during a register transfer.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
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GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.2 Multiword DMA data transfer
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Note: The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined.
Figure 6.1 - Initiating a Multiword DMA Data Burst
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Figure 6.2 - Sustaining a Multiword DMA Data Burst
Note: To terminate the data burst, the Device shall negate DMARQ within the tL of the assertion of the current DIOR_ or DIOW_ pulse. The last data word for the burst shall then be transferred by the negation of the current DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation.
Figure 6.3 - Device Terminating a Multiword DMA Data Burst
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Note: 1. To terminate the transmission of a data burst, the Host shall negate DMACK_ within the specified time after a DIOR_ or DIOW_ pulse. No further DIOR_ or DIOW_ pulses shall be asserted for this burst. 2. If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated.
Figure 6.4 - Host terminating a Multiword DMA Data Burst
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Page 26
GL811S USB2.0 to ATA/ATAPI Bridge Controller 6.4.3 Ultra DMA data transfer
Table 6.5 - Ultra DMA data burst timing requirements
Name Mode 0 (in ns)
min max
Mode 1 (in ns)
min max
Mode 2 (in ns)
min max
Mode 3 (in ns)
min max
Mode 4 (in ns)
Min max
Comment Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations Two cycle time allowing for clock variations Data setup time at recipient Data hold time at recipient Data valid setup time at sender Data valid hold time at sender
t2CYCTYP
240 112 230 15 5 70 6 0 0 20 0 10 20 0 20 70 50 75 160 20 0 20 50 230 150
160 73 154 10 5 48 6 0 0 20 0 10 20 0 20 70 30 70 125 20 0 20 50 200 150
120 54 115 7 5 30 6 0 0 20 0 10 20 0 20 70 20 60 100 20 0 20 50 170 150
90 39 86 7 5 20 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 130 100
60 25 57 5 5 6 6 0 0 20 0 10 20 0 20 55 NA 60 100 20 0 20 50 120 100
tCYC t2CYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV tSR tRFS tRP tIORDYZ tZIORDY tACK tSS
First STORBE time Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release Minimum delay time required for output Drivers to assert or negate Envelope time STROBE to DMARDY_ time Ready to final STROBE time Minimum time to assert STOP or negate DMARQ Maximum time before releasing IORDY Minimum time before driving STROBE Setup and hold times for DMACK_ Time from STROBE edge to negation of DMARQ or assertion of STOP
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Page 27
GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in efficient until DMARQ and DMACK are asserted.
Figure 6.5 - Initiating an Ultra DMA Data-In Burst
Notes: IODD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
Figure 6.6 - Sustained Ultra DMA Data-In Burst
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: 1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY_ is negated. 2. If the tSR timing is not satisfied, the host may receive zero, one, or two more data words from the device.
Figure 6.7 - Host Pausing an Ultra DMA Data-In Burst
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
Figure 6.8 - Device Terminating an Ultra DMA Data-In Burst
(c)2007 Genesys Logic Inc. - All rights reserved.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
Figure 6.9 - Host Terminating an Ultra DMA Data-In Burst
(c)2007 Genesys Logic Inc. - All rights reserved.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
Figure 6.10 - Initiating an Ultra DMA Data-Out Burst
Notes: IODD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the devicet until some time after they are driven by the host.
Figure 6.11 - Sustained Ultra DMA Data-Out Burst
(c)2007 Genesys Logic Inc. - All rights reserved.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY_ is negated. 2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host.
Figure 6.12 - Device Pausing an Ultra DMA Data-Out Burst
(c)2007 Genesys Logic Inc. - All rights reserved.
Page 32
GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
Figure 6.13 - Host terminating an Ultra DMA data-out burst
(c)2007 Genesys Logic Inc. - All rights reserved.
Page 33
GL811S USB2.0 to ATA/ATAPI Bridge Controller
Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
Figure 6.14 - Device Terminating an Ultra DMA Data-Out Burst
6.5 AC Characteristics - USB 2.0
The GL811S conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information.
(c)2007 Genesys Logic Inc. - All rights reserved.
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GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 7 PACKAGE DIMENSION
D D1 D2 D A A2
0.05 S
A1
36 37
25 24
Internal No.
A
E1 E2 E
N : Normal package G : Green package
GL811S
B
AAAAAAAGAA YWWXXXXXXXX
Date Code Lot Code
48 1
e b
Version No.
4X
bbb H A B D
L1
13 12 4X
aaa C A B D
c
01 0
ddd M C A B s D s
C ccc C
SEATING PLANE
02 R1 H R2
0.25mm
GAGE PLANE
S
L
03 -
NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 2. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm.
CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 A2 1.40 1.45 0.053 0.055 0.057 9.00 BASIC 0.354 BASIC D E 9.00 BASIC 0.354 BASIC 0.276 BASIC D1 7.00 BASIC E1 7.00 BASIC 0.276 BASIC 5.50 BASIC D2 0.217 BASIC E2 5.50 BASIC 0.217 BASIC R1 0.08 0.003 0.08 0.20 0.003 0.008 R2 0 0 3.5 7 0 3.5 7 01 0 0 02 11 12 13 11 12 13 03 11 12 13 11 12 13 0.09 0.20 0.004 0.008 c L 0.45 0.60 0.75 0.018 0.024 0.030 1.00 REF 0.039 REF L1 0.20 0.008 S 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION 0.008 aaa 0.20 0.20 0.008 bbb 0.003 ccc 0.08 0.08 0.003 ddd
Figure 7.1 - GL811S 48 Pin LQFP Package
(c)2007 Genesys Logic Inc. - All rights reserved.
Page 35
GL811S USB2.0 to ATA/ATAPI Bridge Controller
D D1 D2 D A A2 A1
48 49
33 32
A
E2 E1 E
InternalNo .
N : Normal package G : Green package
GL811S
B
AAAAAAAGAA YWWXXXXXXXX
Date Code Lot Code
17 1
e 4X b
Version No.
64
bbb H A B D
L1
16 4X
aaa C A B D
0.05 S
c
01 0
ddd M C A B s D s
C ccc C
SEATING PLANE
02 R1 H R2
0.25mm
GAGE PLANE
S
L
03 -
NOTES : 1. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION b DOES NOT INCLUDE DAMBAR 2. PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm.
CONTROL DIMENSIONS ARE IN MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 A 0.006 0.05 0.15 0.002 A1 1.35 1.40 1.45 0.053 0.055 0.057 A2 12.00 BASIC 0.472 BASIC D 12.00 BASIC 0.472 BASIC E 10.00 BASIC 0.393 BASIC D1 10.00 BASIC 0.393 BASIC E1 7.50 BASIC D2 0.295 BASIC 7.50 BASIC 0.295 BASIC E2 0.08 0.003 R1 0.08 0.20 0.003 0.008 R2 0 0 3.5 7 0 3.5 7 0 0 01 02 11 12 13 11 12 13 03 11 12 13 11 12 13 0.008 c 0.09 0.20 0.004 0.45 0.60 0.75 0.018 0.024 0.030 L 1.00 REF 0.039 REF L1 0.008 0.20 S 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BASIC 0.020 BASIC e TOLERANCES OF FORM AND POSITION 0.20 0.008 aaa 0.20 0.008 bbb 0.08 0.003 ccc 0.08 0.003 ddd
Figure 7.2 - GL811S 64 Pin LQFP Package
(c)2007 Genesys Logic Inc. - All rights reserved.
Page 36
GL811S USB2.0 to ATA/ATAPI Bridge Controller
CHAPTER 8 ORDERING INFORMATION
Table 8.1 - Ordering Information
Part Number GL811S-MNGXX GL811S-MSGXX Package 48-pin LQFP 64-pin LQFP Green Green Package Green Package Version XX XX Status Available Available
(c)2007 Genesys Logic Inc. - All rights reserved.
Page 37

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